Low Latency Design of Polar Decoder for Flash Memory

We propose a multiple error correction coding scheme with systematic polar code to enhance the data reliability and to prolong the endurance for flash memory. A line-based 2-bit simplified successive cancellation (SSC) decoder is integrated with a bit-permutation construction to lower the latency. The patterns of information bits and frozen bits are rearranged. The experimental results show that the hardware implementation of the SSC decoder with the codeword permutation speed up 8.1% compared to the prior design.

2021 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW)